In recent years, new or more stringent demands have been imposed on lighting systems, such as increased requirements for energy conservation, and the need to accommodate an increasing variety of different types of lighting units which employ different types of light sources (e.g., incandescent, fluorescent, light emitting diode, etc.) with different driving requirements, with different types of lighting units often being deployed within a same building or even the same room. These demands have driven needs for more options and flexibility in the control of the lighting units within a facility. These needs, in turn, have led to the development and installation of lighting networks within many facilities.
In particular, the lighting industry has developed the Digital Addressable Lighting Interface (DALI) standard for digital communications between the individual components of a lighting system which are connected in alighting network. A wide variety of different DALI devices from different manufacturers can be connected together and integrated into alighting system. This provides a high level of flexibility in configuring alighting system while being assured of interoperability between all of the devices. Control and address capabilities allow a DALI compliant lighting system to individually control the light level of each of the luminaries as well as easily controlling light levels for groups of luminaries.
To maintain this interoperability, the DALI standard imposes requirements on the interfaces of control devices and slave devices for compatibility with other devices on a DALI bus. DALI interfaces are connected to a two-wire differential control/data bus which is common to groups of DALI interfaces. DALI messages are serial data streams and comply with a bi-phase coding, Manchester IEEE 802.3, in which the bit transitions occur between the typical voltage levels of 16 volts (H) and 0 volts (L).
FIG. 1 illustrates the voltage range relationships for the differential two-wire line (a “line-pair”) of a DALI bus (which may sometimes also be referred to as a DALI loop or DALI network). A power source is usually incorporated in the master controller, providing the necessary voltage level on the DALI bus. Each DALI interface receives information by determining the voltage changes representing the bit values, and transmits information by either not clamping or clamping (shorting) the voltage across the two-wire DALI bus.
The DALI standard imposes requirements on the duty cycle of the signals transmitted on a DALI bus. Here, the duty cycle may be considered to be the percentage of time that the transmitted signal is in the “high” state (e.g., corresponding to a logical 1) or conversely, the percentage of time that the transmitted signal is in the “low” state (e.g., corresponding to a logical 0) during a bi-phase encoded data bit. In particular, the duty cycle should lie in a specified range around an ideal 50% duty cycle. The DALI standard also imposes both upper and lower limits on the rise and fall times (edge transitions) of the signals transmitted on a DALI bus. Compliance with these requirements must be ensured by the interface circuits of DALI devices.
To address these requirements, several different communication interface circuits have been developed. In particular, examples of DALI interface circuits are disclosed in: U.S. Patent Application Publication 2004/0225811; U.S. Patent Application Publication 2005/0152440; U.S. Patent Application Publication 2008/0143402; and U.S. Patent Application Publication 2009/0003417.
However, each of these communication interface circuits has certain disadvantages or limitations pertaining to complexity, cost, and/or performance.
Thus, it would be desirable to provide a communication interface circuit which can provide flexible control of the duty cycle of DALI signals without undue complexity and cost. In particular it would be desirable to provide a communication interface circuit which can maintain a duty cycle of DALI signals to be within a specified range, as tight as possible around the ideal 50% value, while taking into account variations in the specified performance of electrical components of the interface circuit. It would further be desirable to provide such a communication interface circuit which can provide flexible control of the rise and fall times of the edge transitions of the DALI signals.